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FEATURES High Speed Version of SMP08 Internal Hold Capacitors Low Droop Rate TTL/CMOS Compatible Logic Inputs Single or Dual Supply Operation Break-Before-Make Channel Addressing Compatible With CD4051 Pinout Low Cost APPLICATIONS Multiple Path Timing Deskew for A.T.E. Memory Programmers Mass Flow/Process Control Systems Multichannel Data Acquisition Systems Robotics and Control Systems Medical and Analytical Instrumentation Event Analysis Stage Lighting Control
INPUT 3
Octal Sample-and-Hold with Multiplexed Input SMP18
FUNCTIONAL BLOCK DIAGRAM
(LSB) A 11 (MSB) C 9 B 10 INH 6 8 DGND 1 OF 8 DECODER 16 VDD SW 13 CH0OUT
SW
14 CH1OUT
SW
15 CH2OUT
SW
12 CH3OUT
SW
1
CH4OUT
SW
5
CH5OUT
GENERAL DESCRIPTION
The SMP18 is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and fast acquisition time. The SMP18 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal to 1/2 LSB in less than 2.5 microseconds. The SMP18's output swing includes the negative supply in both single and dual supply operation. The SMP18 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration make the SMP18 ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters. The SMP18 is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain adjustments. One or more SMP18s can be used with single or multiple DACs to provide multiple set points within a system.
SW
2
CH6OUT
SW HOLD CAPS (INTERNAL)
4 CH7OUT
7 VSS
SMP18
The SMP18 offers significant cost and size reduction over discrete designs. It is available in a 16-pin plastic DIP, a narrow body SO-16 surface-mount SOIC package or the thin TSSOP-16 package. The SMP18 is a higher speed direct replacement for the SMP08.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
ELECTRICAL CHARACTERISTICS
Parameter
Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Source Current Output Sink Current Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE2 Acquisition Time3 Hold Mode Settling Time Channel Select Time Channel Deselect Time Inhibit Recovery Time Slew Rate Capacitive Load Stability Analog Crosstalk SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current Symbol VOS VHS VCH/t ISOURCE ISINK
SMP18-SPECIFICATIONS(@ V
DD = +5 V, VSS = -5 V, DGND = 0 V, RL = No Load, TA = -40 C to +85 C for SMP18F, unless otherwise noted)
Conditions -3 V VIN +3 V TA = +25C, VIN = 0 V -40C TA +85C, VIN = 0 V VIN = 0 V, TA = +25C to +85C VIN = 0 V, TA = -40C TA = +25C, VIN = 0 V VIN = 0 V1 VIN = 0 V1 RL = 20 k
Min
Typ 0.01 2.5 3.5 4 2
Max 10 20 6 8 40 +3.0
Units % mV mV mV mV mV/s mA mA V V V A s s ns ns ns V/s pF dB dB mA
1.2 0.5 -3.0 2.4
VINH VINL IIN tAQ tH tCH tDCS tIR SR
VIN = 2.4 V TA = +25C, -3 V to +3 V to 0.1% To 1 mV of Final Value
0.5 3.5 1 90 45 90 6 500 -72 60 75 5.5
0.8 1
<30% Overshoot -3 V to +3 V Step PSRR IDD VSS = 5 V to 6 V TA = +25C -40C TA +85C
7.5
7.5
9.5
mA
ELECTRICAL CHARACTERISTICS unless otherwise noted)
Parameter Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Source Current Output Sink Current Output Voltage Range Symbol VOS VHS VCH/t ISOURCE ISINK
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = -40 C to +85 C for SMP18F,
Min Typ 0.01 2.5 3.5 4 2 1.2 0.5 0.06 0.06 Max 10 20 6 8 40 10.0 9.5 Limits % mV mV mV mV mV/s mA mA V V
Conditions 60 mV VIN 10 V TA = +25C, VIN = 6 V -40C TA +85C, VIN = 6 V VIN = 6 V, TA = +25C to +85C VIN = 6 V, TA = -40C TA = +25C, VIN = 6 V VIN = 6 V1 VIN = 6 V1 RL = 20 k RL = 10 k
LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE2 Acquisition Time3 Hold Mode Settling Time Channel Select Time Channel Deselect Time Inhibit Recovery Time Slew Rate4 Capacitive Load Stability Analog Crosstalk SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current
VINH VINL IIN tAQ tH tCH tDCS tIR SR
2.4 VIN = 2.4 V TA = +25C, 0 to 10 V to 0.1% To 1 mV of Final Value 0.5 2.5 1 90 45 90 7 500 -72 60 75 6.0 8.0 0.8 1 3.25
V V A s s ns ns ns V/s pF dB dB mA mA
<30% Overshoot 0 V to 10 V Step PSRR IDD 10.8 V VDD 13.2 V TA = +25C -40C TA +85C
8.0 10.0
NOTES 1 Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels. 2 All input control signals are specified with t r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 3 This parameter is guaranteed without test. 4 Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%. Specifications subject to change without notice.
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SMP18
ABSOLUTE MAXIMUM RATINGS PIN CONNECTIONS
CH4OUT 1 CH6OUT 2 INPUT 3 CH7OUT 4
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, 17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, 17 V VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . 20 mA (Not short-circuit protected) Operating Temperature Range FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C Package Type 16-Pin Plastic DIP (P) 16-Pin SOIC (S) 16-Lead TSSOP (RU)
JA* JC
16 VDD 15 CH2OUT 14 CH1OUT
13 CH0OUT TOP VIEW CH5OUT 5 (Not to Scale) 12 CH3OUT INH 6 VSS 7 DGND 8 11 A CONTROL 10 B CONTROL 9 C CONTROL
SMP18
Units C/W C/W C/W Model SMP18FP SMP18FRU SMP18FS
ORDERING GUIDE
76 92 180
33 27 35
NOTES *JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for plastic DIP packages; JA is specified for device soldered to printed circuit board for SOIC and TSSOP packages.
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description Plastic DIP TSSOP-16 SO-16
Package Option N-16 RU-16 R-16A
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP18 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
-3-
SMP18 -Typical Performance Characteristics
100 VDD = +12V VSS = 0V 10 V I N = +6V RL = 10k
5
130 110 DROOP RATE - mV/s VDD = +12V VSS = 0V TA = +85C NO LOAD 90
3
DROOP RATE - mV/s
DROOP RATE - mV/s
1
0
70
-1 VDD = +12V VSS = 0V TA = +25C NO LOAD
50
0.1
-3
30
0.01 -40
-20
0
20
40
60
80
100
-5 0 1 2 3 4 5 67 8 INPUT VOLTAGE - Volts 9 10
10 0 1 2 3 45 6 78 INPUT VOLTAGE - Volts 9 10
TEMPERATURE - C
Droop Rate vs. Temperature
Droop Rate vs. Input Voltage
Droop Rate vs. Input Voltage
0 -1 HOLD STEP - mV VDD = +12V VSS = 0V TA = +25C
HOLD STEP - mV
1 0 -1 -2 -3 -4 -5 VDD = +12V VSS = 0V
30 25
SLEW RATE - V/s
VDD = +12V VSS = 0V TA = +25C NO LOAD
NO LOAD -2
V IN = 6V NO LOAD
20 +SR 15
-3
-4
10
-SR
-5
-6 -7 -55 -35 -15
5
-6 0 1 2 3 45 6 78 INPUT VOLTAGE - Volts 9 10
5
25
45
65
85 105 125
TEMPERATURE - C
0 10
11
12
13 14 15 VDD - Volts
16
17
18
Hold Step vs. Input Voltage
Hold Step vs. Temperature
Slew Rate vs. VDD
4 2 OFFSET VOLTAGE - mV 0 -2 -4 -6 -8 -10 0 1 2 3 45 6 78 INPUT VOLTAGE - Volts 9 10 RL = 20k RL = 10k RL = VDD = +12V VSS = 0V
OFFSET VOLTAGE - mV
20 15 10 5 RL = 0 -5 -10 -15 -20 0 1 2 RL = 10k
VDD = +12V VSS = 0V OFFSET VOLTAGE - mV TA = +85C
4 2 0 -2 -4 -6 -8 -10 RL = 10k RL =
VDD = +12V VSS = 0V TA = -40C
TA = +25C
RL = 20k
RL = 20k
3 45 6 78 INPUT VOLTAGE - Volts
9
10
0
1
2
3 45 6 78 INPUT VOLTAGE - Volts
9
10
Offset Voltage vs. Input Voltage
Offset Voltage vs. Input Voltage
Offset Voltage vs. Input Voltage
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Typical Performance Characteristics-SMP18
0 -1 VDD = +12V VSS = 0V 14 12 VSS = 0V NO LOAD
90 80 REJECTION RATIO - dB 70 60 50 40 30 20 10 -PSRR +PSRR
VDD = +12V VSS = 0V V I N = +6V TA = +25C NO LOAD
OFFSET VOLTAGE - mV
-2 -3 -4 -5 -6 -7 -8 -55 -35 -15
SUPPLY CURRENT - mA
V I N = +5V RL = 10k
10
+85C
8 +25C 6
4
-40C
2 5 25 45 65 85 105 125 4 6 8 10 12 VDD - Volts 14 16 18
TEMPERATURE - C
0 10
100
1k 10k 100k FREQUENCY - Hz
1M
Offset Voltage vs. Temperature
Supply Current vs. VDD
Sample Mode Power Supply Rejection
2 1 0
GAIN - dB
VDD = +6V VSS = -6V TA = +25C NO LOAD
90 45
PHASE SHIFT - Degrees
35 30
VDD = +12V VSS = 0V TA = +25C NO LOAD
0 -45
OUTPUT IMPEDANCE -
25 20 15 10 5 0 10
-1 PHASE -2 -3 -4 -5 100 GAIN
-90 -135 -180 -225 10M
1k
10k 100k FREQUENCY - Hz
1M
100
1k 10k 100k FREQUENCY - Hz
1M
Gain, Phase Shift vs. Frequency
Output Impedance vs. Frequency
15
PEAK-TO-PEAK OUTPUT - Volts
VDD = +6V VSS = -6V TA = +25C NO LOAD REJECTION RATIO - dB
60 50 +PSRR 40 VDD = +12V 30 VSS = 0V TA = +25C 20 NO LOAD 10 HOLD CAPACITORS REFERENCED TO VSS 0 -PSRR
12
9
6
3
0 10k
100k 1M FREQUENCY - Hz
10M
-10 10
100
1k 10k 100k FREQUENCY - Hz
1M
Maximum Output Voltage vs. Frequency
Hold Mode Power Supply Rejection
REV. C
-5-
SMP18
R3 2k R4 1k VCC +15V D1 C1 10F + R1 10 1 2 3 4 5 6 R2 10k R2 10k R2 10k R2 10k 7 8 16 15 14 C2 1F
SMP18
13 12 11 10 9 R2 10k R2 10k R2 10k R2 10k
Burn-in Circuit
APPLICATIONS INFORMATION POWER SUPPLY SEQUENCING
The SMP18, a multiplexed octal S/H, minimizes board space in systems requiring cycled calibration or an array of control voltages. When used in conjunction with a low cost 16-bit D/A, the SMP18 can easily be integrated into microprocessor based systems. Since the SMP18 features break-before-make switching and an internal decoder, no external logic is required. The SMP18 has an internally regulated TTL supply so that TTL/CMOS compatibility is maintained over the full supply range. See Figure 1 for channel decode address information.
POWER SUPPLIES
VDD should be applied to the SMP18 before the logic input signals. The SMP18 has been designed to be immune to latchup, but standard precautions should still be taken.
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)
The SMP18 is capable of operating with either single or dual supplies over a voltage range of 7 to 15 volts. Based on the supply voltages chosen, VDD and VSS establish the output voltage range, which is:
(VSS + 0.06 V ) VOUT (VDD - 2 V )
The buffer offset specification is 10 mV; this is less than 1/2 LSB of an 8-bit DAC with 10 V full scale. The hold step (magnitude of step caused in the output voltage when switching from sample-to-hold mode, also referred to as the pedestal error or sample-to-hold offset) is about 4 mV with little variation over the full output voltage range. The droop rate of a held channel is 2 mV/s typical and 40 mV/s maximum. The buffers are designed to drive loads connected to ground. The outputs can source more than 20 mA over the full voltage range but have limited current sinking capability near VSS. In split supply operation, symmetrical output swings can be obtained by restricting the output range to 2 V from either supply. On-chip SMP18 buffers eliminate potential stability problems associated with external buffers; outputs are stable with capacitive loads up to 500 pF. However, since the SMP18's buffer outputs are not short circuit protected, care should be taken to avoid shorting any output to the supplies or ground.
SIGNAL INPUT (Pin 3)
Note that several specifications, including acquisition time, offset and output voltage compliance, will degrade for supply voltages of less than 7 V. If split supplies are used, the negative supply should be bypassed with a 0.1 F capacitor in parallel with a 10 F to ground. The internal hold capacitors are connected to this supply pin, and any noise will appear at the outputs. In single supply applications, it is extremely important that the VSS (negative supply) pin is connected to a clean ground. The hold capacitors are internally tied to the VSS (negative) rail. Any ground noise or disturbance will directly couple to the output of the sample-and-hold degrading the signal-to-noise performance. The analog and digital ground traces on the circuit board should be physically separated to reduce digital switching noise from entering the analog circuitry.
The signal input should be driven from a low impedance voltage source such as the output of an op amp. The op amp should have a high slew rate and fast settling time if the SMP18's acquisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails (VSS VIN VDD) to avoid the possibility of latchup. If single supply operation is desired, op amps such as the OP183 or AD820 that have input and output voltage compliances including ground, can be used to drive the inputs. Split supplies, such as 7.5 V, can be used with the SMP18.
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SMP18
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW. For analog inputs that may become temporarily disconnected, a resistor to VDD, VSS or analog ground should be used with a value ranging from 200 k to 1 M. Do not apply signals to the SMP18 with power off unless the input current is limited to less than 10 mA.
TYPICAL APPLICATIONS An 8-Channel Multiplexed D/A Converter
Figure 1 illustrates a typical demultiplexing function of the SMP18. It is used to sample-and-hold eight different output voltages corresponding to eight different digital codes from a D/A converter. The SMP18's droop rate of 40 mV/s requires a refresh once every 250 ms before the voltage drifts beyond 1/2 LSB accuracy (1 LSB of an 8-bit DAC is equivalent to 19.5 mV out of a full-scale voltage of 5 V). For a 10-bit DAC the refresh rate must be less than 60 ms, and for a 12-bit system, 15 ms. This implementation is very cost effective compared to using multiple DACs as the number of output channels increases.
+12V
SMP18
13 CH0 +12V VSS 14 CH1 VOA 3 3
REF02
+5V 4 DIGITAL INPUTS VREFA
17 VDD
DAC8228
WR 16 WR ADDRESS BUS ADDRESS DECODE CS 15
VSS 15 CH2
VZ 1 GND 5 VSS A B C
12 CH3 11 10 9 VSS 5 VSS 1 CH4 PIN 9 C 0 0 0 0 1 1 1 1 X
CHANNEL DECODING
PIN 10 B 0 0 1 1 0 0 1 1 X PIN 11 A 0 1 0 1 0 1 0 1 X PIN 6 INH 0 0 0 0 0 0 0 0 1 CH 0 1 2 3 4 5 6 7 NONE PIN 13 14 15 12 1 5 2 4 -
DGND 8 VSS 2 INH 6
CH5
CH6
VSS 4 CH7
VSS 16 +12V 0.1F 7
Figure 1. 8-Channel Multiplexed D/A Converter
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-7-
SMP18
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP (N-16)
0.840 (21.33) 0.745 (18.93)
16 1 9 8
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC
0.015 (0.381) 0.008 (0.204)
0.070 (1.77) SEATING 0.045 (1.15) PLANE
16-Pin (Narrow Body) (SO-16)
0.3937 (10.00) 0.3859 (9.80)
16 1 9 8
0.1574 (4.00) 0.1497 (5.80)
0.2550 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
x 45
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
8 0.0099 (0.25) 0 0.0500 (1.27) 0.0160 (0.41) 0.0075 (0.19)
16-Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
1
8
0.246 (6.25)
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
SEATING 0.0256 PLANE (0.65) BSC
8 0
0.028 (0.70) 0.020 (0.50)
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REV. C
PRINTED IN U.S.A.
C1543a-2-10/96

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